Process Compilation Methods For Thin Film Devices

This book presents a systematic method of automatic generation of fabrication process flows for thin film devices from the schematics of the device structures. According to Prof. Duane S. Boning of MIT, "The work is important: it is the first to define a solid fundamental and mathematical basis for process synthesis." The method combines formal mathematical flow construction methods with a set of library-specific available resources to generate flows compatible with a particular laboratory. It uses a partially ordered set (poset) representation of the device topology. The sequence of fabriction steps is essentially determined from the poset linear extensions. The algorithms have been implemented in a software tool named MISTIC that includes the capability of grading the generated process flows based on the expected device yield and some empirical factors. The compilation procedure has been successfully tested with several conventional Integrated Circuit (IC) and Micro-Electro Mechanical System (MEMS) devices and also circuits using both VLSI and MEMS structures.